1 . Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory device having a high bandwidth and a signal line layout method thereof by achieving a chip architecture formed with multiple input/output lines.
2. Description of Related Art
An important consideration in semiconductor memory design is to select an appropriate architecture. Parameters indicative of the performance of a semiconductor memory are, for example, power consumption, speed, size and the like are typically determined by the architecture. Therefore, the more flexible the chip architecture is, the more the parameters of the semiconductor memory are satisfied sufficiently. Flexibility of a semiconductor memory means that a basic frame can be maintained even though a peripheral circuit is altered or added and the degree of integration increases. Flexibility also means that these variations can occur easily.
Current trends in the industry are the pursuit of both high bandwidth as well as high integration. Furthermore, new memory devices having bandwidth capable of synchronizing with a high system speed instead of with only a simple highly integrated memory device are being developed. There is a need for memory devices in a class with an integrated degree of over 64 Megabit (64 Mb), in particular RAMBUS dynamic RAM or synchronous dynamic RAM having a mother version of 265 Mb dynamic RAM for example, to process 256 data bits in one operating cycle.
In order to satisfy the needs of the industry for memory devices to have a high bandwidth, the architecture of a memory device to be used as mother version of 256 Megabit class should have an internal bandwidth of about 256 bits (one cycle). Currently, the industry designs to satisfy this need are trending toward the development of an architecture which increases the internal bandwidth. Meanwhile, as the degree of integration is raised, the size of a memory chip becomes larger and the loading of each signal line increases. Hence, there are difficulties in reading and writing data.
FIG. 1 illustrates the architecture of 256 Mb memory published in various papers. The configuration of an internal column related circuit based on the architecture shown in FIG. 1 is disclosed in, for example, U.S. Pat. No. 5,247,482, entitled "Semiconductor Memory Device With High Speed Write Operation". When a typical folded bit line structure is adopted, 32K word lines and 16K bit lines are needed to achieve a 256 Mb dynamic RAM. Although not excluding a technique for connecting 512 cells to one bit line in the future, since 256 cells per bit line are generally connected, a 2M array is activated by one word line. Assuming that a refresh cycle is 16K, 2 word lines are enabled in the length direction of a chip by the activation of a row address strobe signal RAS and 8M array is activated in 256 Mb. If the activation is performed as shown in FIG. 1 and two pairs of input/output lines are positioned at a sense amplifier region, the number of data obtained in 2M array is 4 which corresponds to the number of input/output lines. Therefore, 16 data bits are obtained in a 256 Mb device. Since 16 data bits are far fewer than are necessary to achieve an internal bandwidth of 256 bits, it is difficult to obtain a high bandwidth with this architecture. Furthermore, since the line loading of an input/output line and junction loading of gate transistors connecting the input/output line to a bit line is large, a voltage of the input/output line during a read operation is not readily developed. During a write operation, the loading of the input/output line is similarly large and the write operation is performed through a gate transistor of an input/output line in the same way as with the read operation. However, because a data input/output line shown in FIG. 1 is directly connected to the bit line through the gate transistor, the input/output line deteriotates the junction loading and the bit line. Therefore, it has been appreciated by the present inventors that the architecture shown in FIG. 1 is not suitable for a highly integrated memory device having a high bandwidth.
FIG. 2 illustrates another example of the architecture of a semiconductor memory which has reduced line loading and higher data bandwidth as compared with that of FIG. 1. The architecture of FIG. 2 is described in 1991 SYMPOSIUM ON VLSI CIRCUITS, entitled "Circuit Techniques for a Wide Word I/O Path 64 Mega DRAM", pp. 133-134. In FIG. 2, the loading of an input/output line is reduced by the use of a sub input/output line and a local input/output line. Data is transmitted to the local input/output line through a differential amplifier stage by incorporating a predetermined number of sense amplifiers into the sub input/output line. During a write operation, with the architecture of FIG. 2, many NMOS transistors have data transmitted thereby.
FIG. 3 illustrates the path of data input/output in the architecture of FIG. 2. During a write operation, data on the local input/output line is transmitted to transistor 2 by an enable select signal SEC SELECT having column information of a selected block. When a write enable signal YWRITE, which determines the sub input/output line, is enabled, data is transmitted to the sub input/output line through transistor 4. When a bit line information signal S/A SELECT is enabled to select bit lines connected to one sub input/output line, data is transmitted to the corresponding bit line through transistor 10. Consequently, data from the input/output line to the bit line must be transmitted via as many as three NMOS transistors 2, 4, 10 during a write operation. Thus, the architecture of FIG. 2 of a highly integrated memory device with large line loading is disadvantageous.